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ATPG DFT Scan Design Gate-Level Simulation Fault Simulation Python Perl Tcl SDF Mixed-Signal IP Silicon Bring-up Post-Silicon Debug Failure Analysis waveform-debug +9 more Show less

RFIC Design Analog IC Design Mixed-Signal Design Verilog SystemVerilog Python MATLAB Perl Tcl Shell Cadence HFSS RTL Coding Static Timing Analysis DFT SerDes PCIe USB DDR HBM ADC DAC PLL 5G 6G mmWave Signal Processing S-parameters Filter Design Digital Pre-distortion Power Delivery Network SIPI +27 more Show less

C Assembly ARM Git Perforce Verilog RTL Mixed-Signal ISR Computer Architecture Post-silicon bringup System integration Debugging +8 more Show less

C Assembly ARM Git Perforce Verilog RTL Mixed-Signal ISR Computer Architecture Post-silicon bringup Debugging +7 more Show less