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Active Keyword: Engineer, PLL Design Remove filter Clear all

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Senior Engineer, PLL Design

Samsung Semiconductor

San Jose, CA 6 days ago $138,000–$206,000
Actively hiring Confirmed live today Posted this week High trust Below market
PLL Design CMOS Matlab Simulink Verilog SystemVerilog Spectre SpectreRF AMS RF Transceivers SerDes Mixed-Signal Simulation Monte Carlo Analysis Silicon Correlation RTL Design Jitter Budgeting
2+ yrs exp
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Senior Engineer, PLL Design

Samsung Semiconductor

San Jose, CA 19 days ago $138,000–$206,000
Actively hiring Confirmed live yesterday High trust Below market
PLL Design CMOS Matlab Simulink Spectre SpectreRF AMS Verilog SystemVerilog RF Transceivers SerDes Mixed-Signal Simulation Monte Carlo Analysis Silicon Correlation Jitter Budgeting
5+ yrs exp
Save