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Cellular ASIC Design Engineer – Protocols

Apple Inc

San Diego, CA 53 days ago $171,600–$302,200
Actively hiring Verified listing Above market
SystemVerilog Verilog synthesis tools timing analysis tools low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms cellular MAC WiFi MAC IP and TCP/UDP protocols packet buffering queuing scheduling designs security algorithms C SystemC
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Cellular ASIC Design Engineer – Protocols

Apple Inc

San Francisco, CA 53 days ago $181,100–$318,400
Actively hiring Verified listing Above market
SystemVerilog Verilog synthesis tools timing analysis tools low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms cellular MAC WiFi MAC IP and TCP/UDP protocols network infrastructure architecture routers access points switches packet buffering queuing security algorithms AES memory subsystems C SystemC
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Cellular ASIC Design Engineer – Protocols

Apple Inc

San Diego, CA 53 days ago $120,300–$210,100
Actively hiring Verified listing Below market
SystemVerilog Verilog Synthesis tools Timing analysis tools Low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms C SystemC AES Packet buffering Queuing Scheduling Memory subsystems仲裁设计
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Cellular ASIC Design Engineer – Protocols

Apple Inc

San Francisco, CA 53 days ago $126,800–$220,900
Actively hiring Verified listing Below market
SystemVerilog Verilog synthesis tools timing analysis tools low-power design techniques AMBA bus protocols AXI AHB QoS mechanisms cellular MAC WiFi MAC IP and TCP/UDP protocols packet buffering queuing scheduling security algorithms AES memory subsystems C SystemC
Save