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Principal Memory Controller RTL Design Engineer

Microsoft

11 days ago $142,800–$274,800
Actively hiring Verified listing Above market
Verilog SystemVerilog Perl Tcl Python Reed-Solomon-Encoding CHI APB AMBA Synthesis STA CDC_checkers low_power_static_checkers linting_tools
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Memory Control Design Engineer

Qualcomm

San Diego, CA 13 days ago $115,600–$173,400
Actively hiring Below market
Verilog SystemC VHDL RTL UVM C C++ DDR LPDDR PCDDR x86 ARM Synopsys Cadence TCL Mentor Graphics Python Git SVN JIRA Confluence
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Senior Director, BMS/EMPS Controls Design & Strategy

Oracle

44 days ago $141,200–$338,500
Actively hiring Verified listing Above market
BMS EMPS SCADA PLC AWS Kubernetes Terraform Python PostgreSQL CI/CD Docker Prometheus Grafana Ansible Git APIs JSON XML REST GraphQL AI HPC Machine_Learning Digital_Twins Cloud_Infrastructure Industrial_Automation
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ASIC Design Engineer, Cache Controller

Apple Inc

Santa Clara, CA 70 days ago $181,100–$318,400
Actively hiring Above market
RTL Cache PPA ASIC Memory_Systems Multi_Processor_Coherence_Protocols DRAM_Controller SoC Register_Transfer_Level Front_End_Netlist_Analysis Physical_Design_Timing_Closure
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ASIC Design Engineer, Cache Controller

Apple Inc

Santa Clara, CA 70 days ago $147,400–$272,100
Actively hiring Above market
RTL Verilog SystemVerilog Cache Coherence Protocols DRAM Controller PPA Analysis SoC Design ASIC Design Memory Systems High Performance Computing Mentor Graphics Calibre Synopsys DC Compiler Tensilica Diamond Standard Library
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