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Next Gen High-Speed Memory and Cache Controller Design Engineer

Qualcomm

San Diego, CA 20 days ago $101,400–$152,200
Actively hiring Confirmed live today Trusted Below market
ASIC Design RTL LPDDR HBM DDR NoC SRAM Cache Controller x86 ARM Synthesis Timing Closure Gate Level Simulation Power Analysis Physical Design Micro-architecture ISA
3+ yrs exp
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ASIC Design Engineer, Cache Controller

Apple Inc

Santa Clara, CA 89 days ago $129,300–$194,700
Actively hiring Confirmed live today High trust Below market
RTL Micro-architecture SoC Cache Coherence Protocols DRAM Controller Timing Closure Memory Subsystems Interconnect Architectures
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