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Active Keyword: Design Verification Engineer Remove filter Location: Seattle Remove filter Clear all

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Senior ASIC Design Verification Engineer

Nvidia

Santa Clara, CA +5 35 days ago $168,000–$264,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM ASIC Verification Python C/C++ Perl VCS Verdi DFT UPF Machine Learning SoC Functional Coverage Assertion-based Verification GDS
8+ yrs exp Hybrid
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Design Verification Engineer

Apple Inc

Seattle, WA 40 days ago $175,000–$308,500
Actively hiring Confirmed live today Trusted Above market
SystemVerilog UVM Constrained Random Verification Digital Simulation Python Perl C++ Assembly Functional Coverage Code Coverage Assertion Methodology Computer Architecture Digital Design PCI Express DisplayPort MIPI Data Structures and Algorithms
10+ yrs exp
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Design Verification Engineer

Apple Inc

Seattle, WA 40 days ago $122,700–$184,800
Actively hiring Confirmed live today Trusted Below market
SystemVerilog Verilog Python Perl C++ C Assembly Digital Simulation Debug SOC Computer Architecture Digital Design Testbench
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Design Verification Engineer

Apple Inc

Seattle, WA 40 days ago $142,300–$263,300
Actively hiring Confirmed live today Trusted Competitive pay
SystemVerilog UVM Python Perl C++ Assembly Constrained Random Verification Functional Coverage Code Coverage Assertion Methodology Digital Simulation Computer Architecture Data Structures Algorithms PCI Express DisplayPort MIPI VP9 AV1
3+ yrs exp
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