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Active Keyword: SR ASIC Design Engineer Remove filter Location: Santa Clara Remove filter Clear all

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Senior ASIC Design Engineer, NoC & AXI Interconnect

Amd

Santa Clara, CA 161 days ago $200,000–$300,000
Actively hiring Confirmed live today High trust Above market
ASIC Design SystemVerilog Verilog RTL Design Network-on-Chip NoC AXI ACE APB VCS Python Perl Shell Scripting Post-silicon Bring-up Buffer Management
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