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Active Keyword: Power Management IC Design Remove filter Location: Santa Clara Remove filter Clear all

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Staff Engineer, Power Management IC Design

Qualcomm

Santa Clara, CA 40 days ago $159,600–$239,400
Actively hiring Confirmed live today High trust Competitive pay
Cadence ADE Spectre MATLAB Verilog Verilog‑AMS SystemVerilog Simplis SPICE VHDL Control Theory Behavioral Modeling silicon bring‑up Characterization
6+ yrs exp
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Power Management IC Design

Qualcomm

Santa Clara, CA 40 days ago $134,500–$201,700
Actively hiring Confirmed live today High trust Below market
Power Electronics Cadence ADE Spectre MATLAB Verilog Verilog‑AMS SystemVerilog Simplis SPICE VHDL Control Theory Behavioral Modeling Silicon Characterization
4+ yrs exp
Save