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Active Keyword: CPU Physical Design Timing Engineer Remove filter Location: Santa Clara Remove filter Clear all

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CPU Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 34 days ago $209,300–$313,900
Actively hiring Confirmed live today High trust Above market
STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction
6+ yrs exp
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CPU Server Physical Design Timing Engineer

Qualcomm

Santa Clara, CA 35 days ago $175,600–$263,400
Actively hiring Confirmed live today High trust Competitive pay
STA TCL Python Perl PrimeTime Tempus ICC2 Innovus RTL GDS Spice ASIC CTS AOCV POCV Signal Integrity Layout Parasitic Extraction
4+ yrs exp
Save