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R&D Engineer IC Design 4

Broadcom

Austin, TX +1 92 days ago $121,900–$195,000
Actively hiring Confirmed live yesterday High trust Below market
ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis
8+ yrs exp

R&D Engineer IC Design 4

Broadcom

San Jose, CA +1 118 days ago $121,900–$195,000
Actively hiring Confirmed live yesterday High trust Below market
ASIC Design RTL Synthesis Verilog TCL Perl Synopsys Design Compiler Cadence RTL Compiler Formal Verification Synopsys Formality Cadence Conformal Spyglass Lint DFT Scan Methodology Git SVN Timing Analysis Power Analysis
8+ yrs exp