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Active Keyword: PLL Design Remove filter Location: San Jose Remove filter Clear all

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PLL Design/ Integration Senior Staff Engineer

Amd

San Jose, CA 6 days ago $200,000–$300,000
Actively hiring Confirmed live today Posted this week High trust Above market
IC Design Analog/Mixed-Signal PLL FPGA SystemVerilog Vivado ADPLL LDO VCO Clock Synthesis Digital Verification Post-Silicon Validation Device Physics
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Senior Engineer, PLL Design

Samsung Semiconductor

San Jose, CA 22 days ago $138,000–$206,000
Actively hiring Confirmed live today High trust Below market
PLL Design CMOS Matlab Simulink Verilog SystemVerilog Spectre SpectreRF AMS RF Transceivers SerDes Mixed-Signal Simulation Monte Carlo Analysis Silicon Correlation RTL Design Jitter Budgeting
2+ yrs exp
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