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Active Keyword: Lead Design Verification Engineer Remove filter Location: San Jose Remove filter Clear all

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Lead Design Verification Engineer, Memory Controller

Amd

San Jose, CA 16 days ago $200,000–$300,000
Actively hiring Confirmed live 2 days ago High trust Above market
UVM System Verilog Formal Verification Assertion-Based Verification Synopsys VCS Cadence Xcelium JasperGold Questa Formal Gate-Level Simulation Power-Aware Verification DDR5 LPDDR6 HBM4 Network-on-Chip NoC VLSI Silicon Debug
8+ yrs exp
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ASIC Design Verification Engineering Leader

Cisco

San Jose, CA 66 days ago
Actively hiring Confirmed live yesterday High trust
SystemVerilog UVM Verilog Python Perl C++ Linux ASIC Design Formal Verification Jasper Gold Veloce Palladium Zebu HAPS PCIe Ethernet RDMA TCP Fiber Channel P4
10+ yrs exp
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