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Active Keyword: ASIC Design Verification Technical Leader Remove filter Location: San Jose Remove filter Clear all

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ASIC Design Verification Technical Leader

Cisco

San Jose, CA 22 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago Trusted Above market
SystemVerilog UVM ASIC Verification Python Perl Hardware Emulation FPGA Cadence Palladium Siemens Veloce Synopsys ZeBu PCIe Ethernet CXL HBM DDR RTL Silicon Bring-up Post-Silicon Validation
10+ yrs exp
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ASIC Design Verification Engineer, Technical Leader

Cisco

San Jose, CA 38 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago High trust Above market
System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation
8+ yrs exp
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