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Active Keyword: ASIC Design Engineer Technical Lead Remove filter Location: San Jose Remove filter Clear all

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ASIC Design Verification Engineer, Technical Leader

Cisco

San Jose, CA 38 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago High trust Above market
System Verilog UVM ASIC SoC Python Perl PCIe CXL Ethernet AHB AXI DDR Formal Verification Veloce HAPS Simulation Emulation
8+ yrs exp
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ASIC Design Engineer Technical Lead

Cisco

Remote (San Jose, CA) 45 days ago $186,900–$267,700
Actively hiring Confirmed live 2 days ago Low trust Above market
Verilog System Verilog ASIC Design RTL Python Perl TCL Micro-architecture Tape-out post silicon validation Simulation
8+ yrs exp Remote
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