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Active Keyword: Sr. RTL Design Engineer Remove filter Location: Palo Alto Remove filter Clear all

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Senior RTL Design Engineer, Silicon Engineering

SpaceX

Palo Alto, CA 113 days ago $175,000–$280,000
Actively hiring Confirmed live 2 days ago Low trust Above market
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB HDL Simulators EDA Tools Timing Closure Synthesis Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp
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