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Senior RTL Design Engineer

SpaceX

Irvine, CA 113 days ago $165,000$260,000
Actively hiring Confirmed live 2 days ago Low trust Competitive pay
Verilog System Verilog ASIC SoC RTL Design Python AXI AHB Synthesis Timing Closure HDL Simulators EDA Tools Clock Domain Crossing Power Optimization Silicon Bring-up
5+ yrs exp