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Senior Serdes System Design Engineer/Architect

Broadcom

Austin, TX 73 days ago $108,000–$192,000
Actively hiring Verified listing Below market
MATLAB C++ Python RTL Verilog SystemVerilog IEEE 802.3 OIF PCIe DSP Communication Theory Analog Circuit Behavior Transmission Line Theory S-parameters Clock and Data Recovery (CDR) PLLs Equalization Techniques High-speed Serdes
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