Staff IC Verification Engineer

Broadcom

Quick summary

Work type
On-site
Location
Mendota Heights, MN
Salary
$109,700–$175,500 / yr
Posted
7 days ago
Closes
Dec 6, 2026
Nearby
99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $191k
This role $143k
$96k most similar roles pay here $235k

This role pays less than 89% of similar roles. Most pay $165,250–$216,250 — the shaded band above. At the midpoint, this role pays about $143k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 103 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 101 roles with salary data.

Most-posted roles

View all roles at Broadcom

At a glance

TL;DR · Staff IC Verification Engineer

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Broadcom’s ASIC Product Division seeks a senior verification engineer to join its high-performance design team focused on developing advanced subsystems for AI and storage chips. The role involves creating robust verification environments using System Verilog and UVM, designing verification classes such as sequences and agents, implementing coverage and assertions, and developing both random and directed test cases to ensure thorough testing. Daily tasks include analyzing simulation failures and coverage results to enhance design quality. Ideal candidates possess strong expertise in HDL languages like Verilog and SystemVerilog, experience with constrained-random environments using UVM, and proficiency in object-oriented programming techniques such as C++ or Java. The position requires excellent communication skills and the ability to work independently on complex engineering challenges within a matrix organization.

Skills

SystemVerilog UVM Verilog VHDL C++ Java OOP HDL simulators

What you'll do

  • Develop verification environments using System Verilog and UVM techniques.
  • Design verification classes including UVM sequences, agents, scoreboards, and models.
  • Implement coverage and assertions in System Verilog for comprehensive testing.
  • Create random and directed test cases to achieve full coverage of designs.
  • Analyze simulation failures and coverage results to improve design quality.

What we're looking for

  • Proven expertise in System Verilog and UVM for verification environment development
  • Experience designing verification classes including UVM sequences, agents, scoreboards
  • Strong background in HDL languages (Verilog/VHDL) and OOP techniques with C++
  • Demonstrated ability to develop random & directed test cases and analyze coverage results
  • Excellent communication skills and experience working in a matrix organization

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