Staff Engineer, SRAM Layout

Samsung Semiconductor

Quick summary

Work type
On-site
Location
San Jose, CA
Salary
$163,000–$253,000 / yr
Posted
today

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $194k
This role $208k
$149k most similar roles pay here $264k

This role pays more than 65% of similar roles. Most pay $170,000–$218,225 — the shaded band above. At the midpoint, this role pays about $208k versus about $194k for comparable roles.

Based on 240 similar postings.

Employer

About Samsung Semiconductor

Samsung Semiconductor is the global semiconductor business unit of Samsung Electronics, designing and manufacturing memory chips, logic semiconductors, and foundry solutions for a broad range of applications.

Samsung Semiconductor currently has 54 open roles on FindRole.

Listed pay typically runs $163,000–$253,000 across 54 roles with salary data.

Most-posted roles

View all roles at Samsung Semiconductor

At a glance

TL;DR · Staff Engineer, SRAM Layout

Apply Now Log in to save

Join our dynamic team as a Staff Engineer specializing in SRAM Layout, where you will lead the development and execution of full-custom SRAM memory layout and verification flows. You’ll collaborate closely with circuit designers to translate schematics into efficient physical layouts, manage floor planning, placement, routing, and tape-out processes, and optimize designs for area, speed, power, yield, and manufacturability. Utilizing industry-standard EDA tools like Cadence Virtuoso and physical verification software, you will perform rigorous DRC/LVS checks and develop automation scripts in Perl, Tcl, or SKILL to enhance productivity. This role requires extensive experience with advanced process nodes and a strong background in SRAM layout design, coupled with leadership skills to mentor junior engineers and drive best practices within global cross-functional teams.

Skills

Candence_Virtuoso Perl Tcl SKILL DRC LVS ERC RC_Extraction Parasitic_Analysis Signal_Integrity_Verification EDA_Tools Custom_IC_Design Physical_Verification_Pods Project_Management Cross_Functional_Collaboration

What you'll do

  • Lead the development and execution of full-custom SRAM memory layout flows.
  • Translate schematics into efficient, high-performance physical layouts for SRAMs.
  • Design and optimize SRAM layouts at cell, array, and peripheral levels for various metrics.
  • Perform and close all physical verification tasks including DRC, LVS, ERC checks.
  • Develop automation scripts to improve productivity in SRAM layout design.

What we're looking for

  • Extensive experience in SRAM layout design at advanced process nodes.
  • Bachelor's degree with 10+ years of experience or master's with 8+ years.
  • Demonstrated ability to lead and mentor a team of layout engineers.
  • Strong proficiency with industry-standard EDA tools for custom/analog layout.
  • Experience in high-speed, low-power SRAM design in leading-edge nodes.
  • Scripting/automation skills (Perl, Tcl, SKILL) to improve productivity.

Related searches

More Staff Engineer jobs Staff Engineer jobs in San Jose All jobs at Samsung Semiconductor

More like this

Similar roles

Staff Engineer, SRAM Circuit Design

Samsung Semiconductor

San Jose, CA today $163,000–$253,000
HSPICE Python Perl TCL Spectre Cadence Virtuoso FinFET GAA SOI DRC LVS Design for Manufacturability Silicon Debug Voltage Scaling Power Gating Advanced Technology Nodes SRAM Compiler Development
Save

CPU SRAM Design Engineer

Qualcomm

Austin, TX 2 days ago $179,000–$268,400
SRAM Register_File High_Performance_Design Low_Power_Design Semiconductor_Device_Fundamentals Variation_Aware_Simulation Custom_Memory_Layout NanoTime Ansys_EMIR_Analysis ESP_CV Liberate_Power_Analysis Verilog BIST DFT Memory_Analysis_Flow_Development
Save

CPU SRAM Design Engineer

Qualcomm

Austin, TX 2 days ago $122,500–$183,700
SRAM Register_File Circuit_Simulation Monte_Carlo_Analysis Static_Timing_Analysis NanoTime Ansys_EMIR_analysis ESP-CV Liberate_power_analysis Verilog BIST DFT Custom_Memory_Layout Physical_Implementation_Impact Timing_Characterization
Save

Senior SRAM Circuit Design Engineer

Nvidia

Santa Clara, CA 49 days ago $168,000–$264,500
Perl Python Verilog VHDL SPICE Tcl Make RTL Simulation tools Waveform debugging tools ASIC design flow Custom circuit design SRAM design Transistor-level circuit design Power analysis Timing characterization Circuit verification Scripting languages Automation methods
Hybrid
Save

Senior Engineer, DRAM Applications

Samsung Semiconductor

San Jose, CA today $138,000–$206,000
Unix Linux Python Shell DRAM Signal Integrity Power Integrity PCIe Test Automation Data Analysis Server Architecture Networking Kubernetes CI/CD PostgreSQL
Save

Hardware Staff Engineer

Qualcomm

San Diego, CA 54 days ago $134,800–$202,200
Schematic capture Simulation tools Oscilloscopes Logic analyzers Protocol analyzers High-speed digital design Power delivery design Mixed-signal circuit design EMC testing Automotive reliability standards Thermal management Signal integrity analysis Power integrity analysis PCB layout collaboration CI/CD
Save