SOC Design Engineer, ASIC Tools and Methodology Development
Nvidia
At a glance
AI generatedNvidia seeks a Senior SOC/IP Methodology Engineer to join its cutting-edge design team, responsible for developing and optimizing semi-custom RTL to GDS methodologies while collaborating with internal and external partners on SOC/IP requirements. This hands-on role involves traversing from synthesis to final design closure using the latest EDA technologies, ensuring high-quality analysis flows, and driving technical reviews to mitigate risks and improve processes. The ideal candidate has extensive experience in physical design, a master’s degree or equivalent, and over 8 years of relevant industry experience with expertise in Cadence, Synopsys, Mentor tools, and scripting languages like Python, Perl, and Tcl. They must understand full flow integration including DFT and BIST for high-performance designs such as CPUs, GPUs, and machine learning IPs, working closely with Nvidia’s PD design methodology team to integrate external customer IP effectively.
Skills
What you'll do
What we're looking for
Market check
This $168,000–$264,500 range sits above 79% of similar postings on FindRole.
Peer median band
$152,000–$221,800
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$153,043–$216,250
Middle half of comparable postings.
Based on 240 comparable postings.
* 240 is the maximum number of comparable postings sampled.
Employer
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has 802 open roles on FindRole.
Listed pay typically runs $184,000–$287,500 across 798 roles with salary data.
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