SOC IP Methodology Engineer - Custom SOC

Nvidia

Actively hiring
Us, Ca, Santa Clara, US Posted 128 days ago $168,000$264,500 / year

At a glance

AI generated

TL;DR

Nvidia seeks a Senior SOC/IP Methodology Engineer to join its cutting-edge design team, responsible for developing and optimizing semi-custom RTL to GDS methodologies while collaborating with internal and external partners on SOC/IP requirements. This hands-on role involves traversing from synthesis to final design closure using the latest EDA technologies, ensuring high-quality analysis flows, and driving technical reviews to mitigate risks and improve processes. The ideal candidate has extensive experience in physical design, a master’s degree or equivalent, and over 8 years of relevant industry experience with expertise in Cadence, Synopsys, Mentor tools, and scripting languages like Python, Perl, and Tcl. They must understand full flow integration including DFT and BIST for high-performance designs such as CPUs, GPUs, and machine learning IPs, working closely with Nvidia’s PD design methodology team to integrate external customer IP effectively.

Skills

Python Perl Tcl Cadence Synopsys Mentor RTL-to-GDSII EDA IP-XACT DFT BIST ICC2 PT-SI Redhawk Innovus Design Compiler Fusion Compiler CDC LP Checks Genus First Encounter ARM cores Serdes DDR GPU machine learning

What you'll do

  • Develop and optimize semi-custom RTL to GDS methodologies for SOC/IP solutions.
  • Drive technology alignments between internal teams, external collaborators, and IP vendors.
  • Work with customers on SOC/IP development processes and quality assurance requirements.
  • Conduct technical design reviews and mitigate risks in development processes.
  • Perform floorplan experiments to drive area estimates and evaluate solution tradeoffs.
  • Integrate external customer IP into Nvidia designs using best methodologies.

What we're looking for

  • Extensive leadership experience as a methodology and technical expert in physical design.
  • Proven hands-on experience with RTL-to-GDSII tool flows using EDA vendors' tools.
  • Experience handling complex IP ecosystems involving internal and external partners.
  • Strong background in synthesis, CTS, power optimization, placement, and routing methods.
  • Understanding of full flow including DFT and BIST to integrate customer and third-party IPs.
  • Proven abilities to optimize methodology and flows for high productivity and design optimization.
  • Strong scripting skills with Python, Perl, and Tcl.

Market check

Salary context

This $168,000–$264,500 range sits above 79% of similar postings on FindRole.

Peer median band

$152,000$221,800

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$153,043$216,250

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 802 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 798 roles with salary data.

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