Serdes System Design Engineer/Architect

Broadcom

Quick summary

Work type: On-site
Location: Austin, TXIrvine, CASan Jose, CA
Salary: $108,000–$192,000 / yr
Posted: 5 days ago
Closes: Jul 14, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $181k

This role $150k

$95k most similar roles pay here $231k

This role pays less than 78% of similar roles. Most pay $151,475–$209,812 — the shaded band above. At the midpoint, this role pays about $150k versus about $181k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 103 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 101 roles with salary data.

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At a glance

TL;DR · Serdes System Design Engineer/Architect

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This DSP/Systems Design Engineering role within the Physical Layer Products Division involves working with expert communication system/mixed-signal ASIC designers to develop advanced signal processing algorithms for high-speed Serdes at speeds of 100G+. Day-to-day responsibilities include creating channel models and running simulations, developing bit-exact MATLAB and C/C++ system models, and collaborating closely with analog and digital teams to implement designs in silicon. The role also entails lab testing, firmware development, documentation, and supporting marketing efforts. Candidates should have a Bachelors or Masters in Engineering along with extensive experience in communication theory, digital signal processing, and proficiency in MATLAB and C/C++. Knowledge of IEEE standards and hands-on lab skills are essential, while expertise in high-speed Clock and Data Recovery (CDR) PLLs and equalization techniques is highly desirable.

Skills

MATLAB C++ C RTL IEEE 802.3 OIF PCIe Python Git JIRA Confluence Agile Simulation Verification Firmware LabVIEW S-parameter Transmission line theory Analog circuit behavior Clock and Data Recovery (CDR) PLLs Equalization techniques

What you'll do

Develop channel models and run simulations to define Serdes architecture.
Define signal processing block requirements and develop system-level simulation suites.
Create bit-exact MATLAB and C/C++ system models for verification purposes.
Collaborate with design teams to perform vector matching verification using RTL simulations.
Test, debug, and validate firmware associated with physical layer functionality in the lab.

What we're looking for

Expert knowledge in Communication Theory and Digital Signal Processing algorithms.
Experience developing bit-exact MATLAB and C/C++ system models for simulation.
Hands-on lab skills for testing and debugging high-speed Serdes designs.
Proficiency in designing high-speed Clock and Data Recovery (CDR) PLLs.
Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards.
Bachelor's degree in Engineering with 8+ years or Master’s with 6+ years experience.
Expertise in developing and running system-level simulation suites for architectural evaluation.

Similar roles

Senior Serdes System Design Engineer/Architect

Broadcom

Austin, TX +2 83 days ago $108,000–$192,000

MATLAB C++ Python RTL Verilog SystemVerilog IEEE 802.3 OIF PCIe DSP Communication Theory Analog Circuit Behavior Transmission Line Theory S-parameters Clock and Data Recovery (CDR) PLLs Equalization Techniques High-speed Serdes

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