Senior Serdes System Design Engineer/Architect

Broadcom

Quick summary

Work type
On-site
Location
Austin, TX · San Jose, CA · Irvine, CA
Salary
$108,000–$192,000 / yr
Posted
73 days ago
Closes
Aug 22, 2026

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $185k
This role $150k
$94k most similar roles pay here $242k

This role pays less than 75% of similar roles. Most pay $150,084–$220,015 — the shaded band above. At the midpoint, this role pays about $150k versus about $185k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 61 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 60 roles with salary data.

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View all roles at Broadcom

At a glance

TL;DR · Senior Serdes System Design Engineer/Architect

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As a Senior DSP/Systems Design Engineer in the Physical Layer Products Division, you will join an elite team of communication system/mixed-signal ASIC designers working on high-speed Serdes products at speeds exceeding 100G+. Your daily tasks will involve developing advanced signal processing algorithms such as PAM modulation and adaptive equalizers, collaborating with analog and digital teams to implement these in silicon, and validating designs through lab testing. You will also contribute to the development of next-generation wireline communications standards at IEEE and OIF. Key skills include expertise in Communication Theory and Digital Signal Processing, proficiency in MATLAB and C/C++, and hands-on experience with high-speed Clock and Data Recovery (CDR) PLLs. Knowledge of IEEE 802.3/OIF Serdes standards is beneficial.

Skills

MATLAB C++ Python RTL Verilog SystemVerilog IEEE 802.3 OIF PCIe DSP Communication Theory Analog Circuit Behavior Transmission Line Theory S-parameters Clock and Data Recovery (CDR) PLLs Equalization Techniques High-speed Serdes

What you'll do

  • Develop channel models and run simulations to define Serdes architecture.
  • Define signal processing block requirements, architecture, and lab test plans.
  • Create bit-exact MATLAB and C/C++ system models for simulation verification.
  • Evaluate architectural tradeoffs through system-level simulation suites of the Serdes.
  • Test and debug firmware associated with physical layer functionality in Serdes.
  • Conduct lab testing and debugging of high-speed Serdes designs.

What we're looking for

  • Expert knowledge in Communication Theory and Digital Signal Processing algorithms.
  • Experience developing high-speed Clock and Data Recovery (CDR) PLLs.
  • Proficiency in MATLAB and C/C++ programming for system modeling and simulation.
  • Working knowledge of Analog circuit behavior, Transmission line theory, and s-parameter analysis.
  • Hands-on lab skills for testing and debugging Serdes designs.
  • Knowledge of IEEE 802.3/OIF 100G/200G/400G Serdes standards (preferred).
  • Experience in equalization techniques for wireline communication applications.

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