Senior Machine Learning Applications and Compiler Engineer

Nvidia

Confirmed live yesterday High trust
Hybrid

Quick summary

Work type
Hybrid
Location
Santa Clara, CA
Salary
$152,000–$241,500 / yr
Employment
Full-time
Posted
106 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $225k
This role $197k
$137k $293k
below market most similar roles pay here above market

This role pays less than 68% of similar roles. Most pay $196,750–$253,812 — the blue band above. At the midpoint, this role pays about $197k versus about $225k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Machine Learning Applications and Compiler Engineer

JOB TITLE: Senior Machine Learning Applications and Compiler Engineer, LPX The Senior Machine Learning Applications and Compiler Engineer joins the team to develop algorithms and optimizations for the LPX inference and compiler stack. This role involves building and maintaining high-performance runtime and compiler components to map large-scale inference workloads onto NVIDIA systems. Key responsibilities include defining mappings for neural network graphs, extending software ecosystems, and benchmarking performance metrics. The engineer will prototype compilation techniques like graph transformations and memory optimizations for spatial processors while collaborating with hardware architects. Required skills include proficiency in C/C++, Rust, and LLVM or MLIR, alongside experience with TensorFlow, PyTorch, and ONNX. The work focuses on solving deep learning inference challenges by optimizing software-hardware co-design for GPUs and domain-specific spatial accelerators.

What you'll do

  • Build and maintain high-performance runtime and compiler components for end-to-end inference optimization.
  • Implement mappings of large-scale inference workloads onto NVIDIA systems.
  • Integrate with NVIDIA’s software ecosystem to contribute to libraries, tooling, and deployment interfaces.
  • Benchmark and profile performance metrics to ensure efficient neural network graph mappings to hardware.
  • Provide software feedback to hardware architects to influence future architecture designs and features.
  • Prototype new compilation techniques including graph transformations, scheduling strategies, and memory optimizations.
  • Publish and present technical work on novel compilation approaches at top-tier ML and architecture venues.

What we're looking for

  • MS or PhD in Computer Science, Electrical/Computer Engineering, or related field, or equivalent experience.
  • 5 years of relevant experience.
  • Proficiency in systems level programming (e.g., C/C++ and/or Rust) and solid CS fundamentals in data structures, algorithms, and concurrency.
  • Hands-on experience with compiler or runtime development, including IR design, optimization passes, or code generation.
  • Experience with LLVM and/or MLIR, including building custom passes, dialects, or integrations.
  • Familiarity with deep learning frameworks such as TensorFlow and PyTorch, and experience working with portable graph formats such as ONNX.
  • Solid understanding of parallel and heterogeneous compute architectures, such as GPUs, spatial accelerators, or other domain specific processors.
  • Direct experience with MLIR based compilers or other multilevel IR stacks, especially in the context of graph based deep learning workloads (preferred).

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