Senior Director, Board Product Development Engineering

Nvidia

Confirmed live yesterday High trust

Quick summary

Work type
On-site
Location
Santa Clara, CA
Salary
$332,000–$500,250 / yr
Employment
Full-time
Posted
49 days ago
Freshness
Confirmed live yesterday

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $252k
This role $416k
$159k most similar roles pay here $537k

This role pays more than 99% of similar roles. Most pay $215,050–$288,650 — the shaded band above. At the midpoint, this role pays about $416k versus about $252k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1391 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1116 roles with salary data.

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View all roles at Nvidia

At a glance

TL;DR · Senior Director, Board Product Development Engineering

Senior Director, Board Product Development Engineering leads a global organization across three technical pillars: PCB & Fab, SMT/PCBA, and High-Speed Connector & Signal Integrity. This role focuses on the integration of advanced datacenter board products, ensuring manufacturing and test readiness from chip to board. The successful candidate will design and institutionalize integration processes, manage warpage-tolerant DFM, control impedance and CTE for high-speed stackups, and oversee reliability and yield performance across the production chain. Key responsibilities include coordinating cross-domain handoffs, defining entry and exit requirements at domain boundaries, and collaborating with partners like CM, ODM, and OSAT to qualify new fabrication methods. Required expertise includes advanced packaging, flip-chip BGA, high-density PCB fabrication, SMT assembly, and signal integrity testing using BERT and channel margining to solve complex manufacturing challenges for next-generation datacenter hardware.

What you'll do

  • Design and implement the integration readiness process for next-generation datacenter board products to ensure manufacturing and test success.
  • Lead a global Board PDE organization across PCB fabrication, SMT/PCBA, and high-speed connector/signal integrity pillars.
  • Define entry and exit requirements at each domain boundary to ensure seamless handoffs between chip, PCB, and assembly stages.
  • Manage technical constraints including warpage-tolerant DFM, reflow for BGA pitch, and impedance control for high-speed stackups.
  • Collaborate with test engineering teams to establish manufacturing test flow requirements and develop diagnostic boards.
  • Investigate production excursions to identify root causes and address design gaps with factory planning and design teams.
  • Manage relationships with manufacturing partners including CMs, ODMs, and OSATs to qualify new fabrication methods for high-volume production.
  • Serve as the primary chip-to-board representative across NVIDIA’s operations, engineering, and executive leadership teams.

What we're looking for

  • BS in Electrical Engineering, Materials Science, or a related technical field (MS or PhD preferred).
  • Experience in product, manufacturing, or operations engineering for high-complexity electronics.
  • 8+ years of experience leading engineering teams and 5+ years leading leaders in a global, cross-matrixed organization.
  • Proven track record of taking complex board and system products from design through NPI to high-volume manufacturing.
  • Comprehensive technical knowledge of the chip-to-board stack including advanced packaging, PCB fabrication, SMT, and assembly.
  • Expertise in high-speed signal integrity and manufacturing testing, including BERT and channel margining.
  • Ability to communicate complex technical information clearly to both technical and non-technical executive audiences.
  • Experience with AI or datacenter platforms, next-gen interconnects, and 2.5D/3D packaging (preferred).

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