below marketmost similar roles pay hereabove market
This role pays more than
82%
of similar roles. Most pay
$171,000–$235,750
— the blue band above.
At the midpoint, this role pays about
$236k
versus about
$203k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
1623 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 1110 roles with salary data.
The Senior DevTech Compute Engineer, Compression and Data Processing joins the Developer Technology Compute team to prototype and develop groundbreaking methods for accelerating complex distributed workflows. You will build novel approaches for GPU-accelerated dataframe analytics, high-throughput low-latency lossless and lossy compression, and transactional or vector databases. Daily responsibilities include performing in-depth analysis of data-intensive workloads, optimizing performance across heterogeneous GPU/CPU architectures, and influencing next-generation hardware designs and programming models. Required skills include fluency in C/C++, low-level parallel programming using CUDA, ROCm, Metal, OpenACC, OpenMP, MPI, pthreads, or TBB, and expertise in memory subsystems, caches, and NICs. You will solve technical problems regarding "on-the-wire" compression, late materialization, and memory management to enable low-latency queries across massive data lakes.
Prototype and integrate novel GPU-accelerated methods for distributed data processing and dataframe analytics.
Develop high-throughput, low-latency advanced lossless and lossy compression methods.
Perform in-depth analysis and optimization of complex data-intensive workloads for heterogeneous GPU/CPU architectures.
Influence the design of next-generation hardware architectures, software components, and programming models.
Work with customers and CSPs to integrate solutions at Speed-Of-Light and influence open standards.
Investigate and overcome system-level bottlenecks for multi-stage and multi-IP overlapped workloads.
Co-design systems and hardware blocks to define the next frontier for distributed data processing.
What we're looking for
Masters or PhD in Computer Science, Computer Engineering, Applied Math, or a related computationally focused science degree (or equivalent experience).
At least 5+ years of relevant work or research experience in state-of-the-art systems or complex projects.
Hands-on experience with low-level parallel programming across execution units such as CUDA, ROCm, Metal, OpenACC, OpenMP, MPI, pthreads, or TBB.
Fluency in C/C++, algorithms, and data structures.
Knowledge of accelerator architecture fundamentals, including memory subsystems, caches, NICs, and storage I/O.
Domain expertise in data processing, compression/decompression, codecs, high-performance distributed databases, ETL, or data analytics.
PhD or a recent project/publication in a relevant field (preferred).
Background in compression, video/image codecs, low-latency data analysis, storage systems, networking, or distributed computer architectures (preferred).
C++
C
CPU Architecture
x86
ARM
GPU Architecture
Parallel Programming
Vectorization
CPU Intrinsics
Concurrent Data Structures
Spark
HPC
Accelerated Computing
Memory Subsystem
Algorithms
C++
C
CUDA
OpenACC
OpenMP
MPI
pthreads
Deep Learning
Machine Learning
Parallel Programming
GPU Architecture
HPC
Computer Vision
Natural Language Processing
Linear Algebra
Performance Optimization
Deep Learning
Machine Learning
C++
CUDA
GPU Architecture
Parallel Programming
OpenMP
MPI
pthreads
LLMs
Computer Vision
Linear Algebra
Performance Optimization
Multimodal Architectures
C
Software Development