Senior Deep Learning Compiler Engineer, HW-SW Codesign

Nvidia

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Remote

Quick summary

Work type: Remote
Location: Santa Clara, CAAustin, TXRedmond, WA
Salary: $152,000–$241,500 / yr
Employment: Full-time
Posted: 42 days ago
Freshness: Confirmed live today
Nearby: 99+ roles within 25 mi

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Competitive pay

How this pay compares to similar roles

Similar $207k

This role $197k

$141k $257k

below market most similar roles pay here above market

This role pays less than 55% of similar roles. Most pay $177,287–$235,750 — the blue band above. At the midpoint, this role pays about $197k versus about $207k for comparable roles.

Based on 240 similar postings.

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About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 1623 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 1110 roles with salary data.

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At a glance

TL;DR · Senior Deep Learning Compiler Engineer, HW-SW Codesign

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The Senior Deep Learning Compiler Engineer - HW-SW Codesign joins the XLA team to develop compiler optimization algorithms for deep learning workloads. The role involves optimizing inference and training performance for the JAX framework and the OpenXLA compiler on NVIDIA GPUs at scale. Key responsibilities include crafting compiler optimization techniques for deep learning network graphs, designing novel graph partitioning and tensor sharding techniques for distributed training, and performing performance tuning and analysis. The engineer will perform code-generation for NVIDIA GPU backends using MLIR, LLVM, and OpenAI Triton. Required skills include C/C++ programming, performance analysis, and a strong foundation in CPU and GPU architecture. The work focuses on accelerating next-generation deep learning software and designing AI compiler software features for future hardware.

Skills

C++ CUDA XLA MLIR LLVM OpenAI Triton JAX PyTorch TensorFlow TVM OpenCL Distributed Programming High-Performance Computing Compiler Optimization Deep Learning Frameworks

What you'll do

Develop compiler optimization algorithms for deep learning workloads.
Optimize inference and training performance for the JAX framework and OpenXLA compiler.
Implement compiler optimization techniques for deep learning network graphs.
Design novel graph partitioning and tensor sharding techniques for distributed training.
Perform performance tuning and analysis for NVIDIA GPUs at scale.
Generate code for NVIDIA GPU backends using MLIR, LLVM, and OpenAI Triton.
Design user-facing features in JAX and related libraries.
Design AI compiler software features for next-generation GPUs with hardware engineering teams.

What we're looking for

Bachelor's, Master's, or Ph.D. in Computer Science, Computer Engineering, a related field, or equivalent experience.
4+ years of relevant work or research experience in performance analysis and compiler optimizations.
Excellent C/C++ programming and software design skills, including debugging, performance analysis, and test design.
Strong foundation in architecture of CPU, GPUs, or other high-performance hardware accelerators.
Knowledge of high-performance computing and distributed programming.
CUDA or OpenCL programming experience (preferred).
Experience with XLA, TVM, MLIR, LLVM, OpenAI Triton, deep learning models, and framework design (preferred).
Experience working with deep learning frameworks such as JAX, PyTorch, or TensorFlow (preferred).

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