RFIC Layout Engineer

Apple Inc

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Quick summary

Work type
On-site
Location
Irvine, CA
Salary
$118,019–$207,100 / yr
Posted
2 days ago
Freshness
Confirmed live today
Nearby
99+ roles within 25 mi

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Salary context

Below market

How this pay compares to similar roles

Similar $195k
This role $163k
$104k $249k
below market most similar roles pay here above market

This role pays less than 74% of similar roles. Most pay $162,559–$227,500 — the blue band above. At the midpoint, this role pays about $163k versus about $195k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3499 open roles on FindRole.

Listed pay typically runs $166,600–$277,600 across 2707 roles with salary data.

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At a glance

TL;DR · RFIC Layout Engineer

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JOB TITLE: RFIC Layout Engineer The RFIC Layout Engineer joins the Wireless SoC Radio Team to research, design, and bring next-generation wireless technologies into high-volume production using advanced CMOS technology nodes. This role involves performing detailed transistor-level layout for RF and analog circuit blocks, including LNAs, mixers, PLLs, modulators, power amplifiers, and data converters. Key responsibilities include block-level layout through full verification flows involving extraction, DRC, LVS, and DFM checking, as well as collaborating on floorplanning and reviewing power routing, electromigration, and signal coupling. Candidates must possess FinFet experience and proficiency in CADENCE layout tools. Preferred skills include knowledge of deep sub-micron CMOS, RC delay, and high-frequency routing, alongside scripting abilities in PERL or SKILL to support the development of energy-efficient radios from RF to bits.

Skills

RFIC Layout CMOS FinFET LNA Mixers PLL ADC DAC DRC LVS ERC DFM CALIBRE CADENCE PERL SKILL RC Delay Electromigration

What you'll do

  • Perform detailed transistor-level layout for RF and analog blocks like LNAs, mixers, and PLLs.
  • Execute block-level layout through full verification flows including extraction, DRC, LVS, and DFM checking.
  • Collaborate with designers to develop block-level floorplans.
  • Review layouts for power/ground routing, electromigration, and signal path integrity.
  • Ensure differential and IQ matching and minimize signal coupling.
  • Apply layout techniques for device matching, parasitic minimization, and RF shielding.
  • Interpret CALIBRE DRC, ERC, and LVS results in FinFet technology.

What we're looking for

  • Minimum requirement of a bachelor's degree.
  • Experience with FinFet technology.
  • Experience in custom RF/analog layout for radio transceivers with extensive knowledge of deep sub-micron CMOS (preferred).
  • Knowledge of layout techniques for device matching, minimizing parasitics, RF shielding, and high frequency routing (preferred).
  • Solid understanding of RC delay, electromigration, and coupling (preferred).
  • Understanding of guard rings, DNW, PN junctions, and advanced process effects such as LOD and WPE (preferred).
  • High level proficiency in interpretation of CALIBRE DRC, ERC, LVS in FinFet Technology (preferred).
  • Knowledge of CADENCE layout tools (preferred).

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