RFIC Layout Engineer

The RFIC Layout Engineer joins the Wireless SoC Radio Team to design and bring next-generation wireless technologies into high-volume production using advanced CMOS technology nodes. Working closely with the RFIC design team, you will perform detailed transistor-level layout and verification for complex SoC products, including blocks such as LNAs, mixers, PLLs, power amplifiers, and data converters. Your daily responsibilities involve block level floorplanning, extraction, DRC, LVS, and DFM checking while managing power routing, electromigration, and signal coupling. You will utilize Cadence layout tools and may employ PERL or SKILL scripting. The role requires expertise in deep sub-micron CMOS, FinFET technology, and advanced techniques for device matching, RF shielding, and high frequency routing to solve critical challenges in radio transceiver design and integrated circuit development.