This role pays more than
93%
of similar roles. Most pay
$182,000–$238,162
— the shaded band above.
At the midpoint, this role pays about
$300k
versus about
$210k
for comparable roles.
Based on 240 similar postings.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
904 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 886 roles with salary data.
As a Principal EDA R&D Engineer, you will join the team to pioneer next-generation hardware formal verification tools. You will lead the research, architecture, and development of core formal verification engines enhanced by Agentic AI frameworks. Your daily responsibilities include constructing new algorithms for Model Checking, SAT/SMT solvers, BDDs, Equivalence Checking, and Theorem Proving. You will build multi-agent AI systems using LLMs, Reinforcement Learning, and Graph Neural Networks to automate RTL topology analysis and partition large design spaces. The role requires expert proficiency in C/C++ (Modern C++17/20), experience with Agentic AI pipelines like LangChain or AutoGen, and knowledge of System Verilog, VHDL, and Verilog. You will solve complex verification challenges by developing orchestration layers to bypass state-space explosion while automating the generation of System Verilog Assertions from natural language specifications.
Architect and develop new formal verification algorithms including Model Checking, SAT/SMT solvers, and Equivalence Checking.
Design and deploy multi-agent AI systems using LLMs and Reinforcement Learning to analyze RTL topologies.
Build orchestration layers where autonomous AI agents collaborate to manage large design spaces and bypass state-space explosion.
Develop engines to automatically generate complex System Verilog Assertions from natural language specifications.
Implement high-performance C/C++ code for production-grade EDA tool suites.
Automate the partitioning of large designs and the dynamic tuning of solver parameters.
Translate algorithmic research into scalable features for multi-billion-gate hardware builds.
What we're looking for
Ph.D. or Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a related quantitative field.
Minimum of 15 years of professional R&D experience building commercial or advanced academic EDA hardware verification tools.
Deep mathematical and hands-on understanding of formal methods including BMC, PDR/IC3, abstract interpretation, and theorem proving.
Expert-level proficiency in C/C++ (Modern C++17/20) with a focus on high-performance data structures and memory optimization.
Proven experience building or researching Agentic AI pipelines, multi-agent frameworks, tool-use execution, and prompt engineering for hardware descriptions.
Experience with RTL languages including SystemVerilog, VHDL, and Verilog combined with a solid understanding of SystemVerilog Assertions (SVA).
Track record of successfully deploying world-class EDA solutions in high-stakes environments (preferred).
Experience establishing innovative answers to complex verification challenges (preferred).
System Verilog
UVM
SVA
Verilog
VCS
Questa
Perl
Tcl
Make files
Gate Level Simulation
Formal Equivalence
LLMs
Agentic AI Frameworks
Mixed Signal Design
Functional Coverage
Co-simulation
Wireless Communications
Signal Processing
RF Design
MIMO
OFDM
C++
MATLAB
Python
FPGA
Mesh Networking
Channel Modeling
Digital Communication
Prototyping
Medical Device Design Controls
Risk Management
FDA
ISO
IEC
EN
Design for Six Sigma
SolidWorks
CAD
Injection Molding
Microsoft Project
Verification and Validation
SOPs
Change Management