Lead Software Engineering, C++

JPMorgan Chase

Quick summary

Work type: On-site
Location: London, United Kingdom
Posted: 3 days ago
Nearby: 63 roles within 25 mi

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How this pay compares to similar roles

Similar $175k

$133k most similar roles pay here $217k

This listing doesn't post a salary. Most similar roles pay $141,175–$208,863.

Based on 240 similar postings.

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About JPMorgan Chase

JPMorgan Chase & Co. is a global financial services firm and one of the largest banks in the world, offering investment banking, commercial banking, asset management, and consumer financial services.

JPMorgan Chase currently has 436 open roles on FindRole.

Listed pay typically runs $152,000–$215,000 across 230 roles with salary data.

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At a glance

TL;DR · Lead Software Engineering, C++

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As a Lead Software Engineering - C++ in the Electronic Trading Technology team at JPMorgan Chase, you will lead the design and development of market gateway solutions with hardware FPGA acceleration. Your day-to-day responsibilities include driving software development cycles to optimize latency and reliability, collaborating closely with hardware engineering teams to integrate FPGA pipelines into your C++ software stack, and ensuring high operational excellence. You’ll work on critical trading connectivity and risk management applications used globally, requiring a deep understanding of modern C++, Unix/Linux environments, and multithreading principles. Additionally, you must have hands-on experience in system design, application development, testing, and maintaining stability in production settings, along with scripting skills in Python, Perl, or Shell for automation tasks. This role demands expertise in low latency design using DMA, exchange connectivity, and pre-trade risk systems, as well as familiarity with FPGA development for financial applications, PCI Express, TCP/IP sockets, and integrating C++, Verilog, and VHDL solutions in Linux environments.

Skills

C++ Unix/Linux Python Perl Shell Agile CI/CD TCP/IP PCI Express FIX SBE DMA FPGA Verilog VHDL

What you'll do

Design and develop high-quality C++ code for trading connectivity and risk controls.
Implement end-to-end low latency client setups including production rollout and validation.
Integrate FPGA pipelines with C++ software to ensure deterministic performance.
Establish and execute test strategies focusing on latency, throughput, and resiliency.
Lead the development of market access trading and risk management modules.

What we're looking for

Proficiency in modern C++ on Unix/Linux with strong multithreading and object-oriented design fundamentals.
Hands-on experience in system design, application development, testing, and operational stability in production environments.
Advanced understanding of Agile methodologies, including CI/CD, resiliency, and security.
Demonstrated experience in low latency design and development using C/C++, DMA, exchange connectivity, and pre-trade risk systems.
Exposure to FPGA development for financial industry applications, including embedded software and kernel driver development.
Proficiency with PCI Express, TCP/IP sockets, L1/L3 switches, and integrating C++, Verilog, and VHDL solutions in Linux environments.
Experience implementing and certifying exchange connectivity using FIX, SBE, and native binary protocols.

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