Lead ATE Test Development Engineer - LPU

Nvidia

Actively hiring
Santa Clara, US Posted 30 days ago $196,000–$310,500 / year
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At a glance

AI generated

TL;DR

NVIDIA seeks a Lead ATE Test Development Engineer to join its LPU team, requiring extensive experience in IC design and VLSI testing. This senior role involves leading the definition, development, and implementation of ATE test programs for new silicon products, ensuring efficient transfer from design engineering to mass production. Key responsibilities include enhancing test coverage, collaborating with SLT and system validation teams to replicate system-level failures on ATE, and working closely with architects and designers to improve field reliability. Essential skills encompass hands-on experience with Advantest 93K ATE platforms, knowledge of DFT techniques like SCAN and ATPG, and proficiency in Linux, Perl/Python, and C/C++. Ideal candidates will have a background in high-power SOC deployment and expertise in yield analysis and defect characterization, contributing to the development of cutting-edge server products.

Skills

Advantest 93K Perl Python C C++ Java Linux DFT SCAN ATPG MBIST IOBIST Signal Integrity Power Integrity System Level Testing Yield Analysis Vmin/Fmax Characterization Defect Analysis

What you'll do

  • Define, develop, implement, and support ATE test programs for new silicon products.
  • Streamline test program development to enhance coverage and reduce DPPM on ATE.
  • Collaborate with SLT and system validation teams to replicate system-level failures on ATE.
  • Work with cross-functional teams to debug product failures and improve field reliability.
  • Develop test methods and strategies to increase production yields and reduce costs.

What we're looking for

  • 12+ years of relevant experience in IC Design, application or ATE testing of VLSI.
  • Bachelor’s Degree or higher in Electrical Engineering/Computer Engineering (or equivalent).
  • Hands-on experience with Advantest 93K ATE platform (SmarTest 7 and 8).
  • Strong critical thinking, communication, and collaboration skills.
  • Expertise in DFT insertion techniques including SCAN, ATPG, MBIST, and IOBIST.
  • Knowledge of test hardware design for signal and power integrity.
  • Experience with system level testing/validation and product engineering.

Market check

Salary context

This $196,000–$310,500 range sits above 95% of similar postings on FindRole.

Peer median band

$132,000–$207,540

Median floor and ceiling across peers.

Typical midpoint (25–75%)

$140,931–$195,581

Middle half of comparable postings.

Based on 240 comparable postings.

* 240 is the maximum number of comparable postings sampled.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 801 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 797 roles with salary data.

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