Integration Engineer

Apple Inc

Quick summary

Work type: On-site
Location: Santa Clara, CA
Salary: $126,800–$190,900 / yr
Posted: 52 days ago
Nearby: 99+ roles within 25 mi

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $157k

This role $159k

$116k most similar roles pay here $200k

This role pays more than 56% of similar roles. Most pay $126,237–$186,862 — the shaded band above. At the midpoint, this role pays about $159k versus about $157k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 1723 open roles on FindRole.

Listed pay typically runs $162,500–$272,100 across 1398 roles with salary data.

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At a glance

TL;DR · Integration Engineer

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The Integration Engineer role within the Hardware team requires a candidate with experience in ASIC design to integrate third-party or internal IP blocks into SoCs, manage RTL codebases, and ensure proper connectivity and bus protocols. Responsibilities include creating top-level SoC RTL, maintaining build and test infrastructure, defining synthesis constraints, collaborating on timing closure, and supporting functional verification teams. The ideal candidate will have a solid understanding of digital logic design using SystemVerilog or Verilog, familiarity with Synopsys and Cadence tools, knowledge of bus protocols like AXI and AHB, and scripting skills in Python, Perl, TCL, and Shell for automation tasks. This role involves working on large-scale SoC projects where precision and attention to detail are crucial for design quality and timing closure.

Skills

SystemVerilog Verilog Synopsys Cadence AXI AHB APB PCIe USB DDR Python Perl TCL Shell CI/CD

What you'll do

Integrate third-party or internal IP blocks into a SoC.
Manage and merge RTL codebases to ensure correct bus/interface protocols.
Create and maintain top-level SoC RTL, wrappers, and interconnects.
Develop and maintain automated build and regression systems for integration.
Define and validate synthesis and timing constraints (SDC files).
Work closely with physical design teams to achieve timing closure at the top level.
Provide functional verification support including simulation bring-up and debug.

What we're looking for

Experience in IP and RTL integration for SoC design.
Expertise in creating and maintaining top-level SoC RTL, wrappers, and interconnects.
Proficiency in linting, synthesis, and timing closure processes.
Development of automated build and regression systems for integration.
Knowledge of digital logic design and familiarity with SoC design tools.
Strong scripting skills (Python, Perl, TCL, Shell) for automation tasks.

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