IC Design AI/ML Silicon Debug & Yield Engineer

Broadcom

Quick summary

Work type: On-site
Location: Irvine, CASan Jose, CA
Salary: $108,000–$192,000 / yr
Posted: 113 days ago
Closes: Aug 17, 2026
Nearby: 99+ roles within 25 mi

Market check

Salary context

Below market

How this pay compares to similar roles

Similar $196k

This role $150k

$93k most similar roles pay here $250k

This role pays less than 89% of similar roles. Most pay $168,862–$222,425 — the shaded band above. At the midpoint, this role pays about $150k versus about $196k for comparable roles.

Based on 240 similar postings.

Employer

About Broadcom

Broadcom is a global semiconductor and infrastructure software company that designs and markets a wide range of networking, storage, and wireless connectivity solutions. Industry: Semiconductors & Infrastructure Software

Broadcom currently has 103 open roles on FindRole.

Listed pay typically runs $120,000–$192,000 across 101 roles with salary data.

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At a glance

TL;DR · IC Design AI/ML Silicon Debug & Yield Engineer

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Join our dynamic team as a senior AI-driven yield engineer responsible for building an end-to-end silicon diagnostic pipeline. You will process massive volumes of scan failure data and parameters using advanced AI methodologies to identify critical issues affecting yield. Key responsibilities include developing ML models for automated classification of scan failures, integrating high-dimensional data for predictive yield modeling, conducting holistic yield analysis, orchestrating cutting-edge EDA tools, and leading cross-functional teams to ensure alignment between design, manufacturing, and testing processes. Ideal candidates possess deep knowledge in ASIC design, DFT, and semiconductor manufacturing, along with expertise in Python (Pandas, Scikit-Learn), big data environments like Spark, and industry-standard yield management systems.

Skills

Python Pandas Scikit-Learn PyTorch TensorFlow SQL Spark Snowflake AI/ML EDA tools CI/CD FinFET Deep Sub-micron effects Pattern Recognition Clustering Regression models PDF Solutions Synopsys YieldExplorer Cadence Clarity

What you'll do

Develop and deploy ML models to automate classification of scan failures.
Integrate high-dimensional data to predict yield excursions before production.
Analyze interplay between design marginalities, voltage scaling, and manufacturing variations.
Evaluate and implement AI-based EDA tools for root-cause analysis.
Serve as a translator between Fab, Design, and Test teams using data insights.

What we're looking for

Deep understanding of ASIC design including logic circuits, memory, DFT, and yield engineering.
Expertise in AI/ML tools like Python (Pandas, Scikit-Learn), PyTorch/TensorFlow for data analysis.
3+ years experience in silicon debug, DFT, or yield engineering with knowledge of FinFET effects.
Proficiency in pattern recognition, clustering, and regression models for defect analysis.
Familiarity with industry-standard yield management systems such as Synopsys YieldExplorer.

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