Hardware Developer, EDA

What you'll do

• Customize Cadence graphical user interfaces using the Cadence SKILL programming language.
• Apply SystemVerilog and UVM methodologies to validate chip functionality and perform functional coverage analysis.
• Conduct EDA analysis for large scale SoC designs including noise, timing, power integrity, and electromigration.
• Manage timing constraints and define mitigation strategies through design optimization and Tcl-based tool enhancements.
• Develop VLSI design tools for hierarchical integration, floor planning, and power optimization.
• Maintain and enhance complex EDA codebases for power analysis and power grid analysis.
• Lead a team to analyze, maintain, and enhance EDA software toolkits.
• Apply AI, machine learning, and large language model techniques to EDA specific workflows.

What we're looking for

• Master’s degree in Computer Science, Computer Engineering, or a related field.
• Bachelor's degree plus five years of progressive experience in lieu of a Master's degree.
• One year of experience as an Engineer or in a related role.
• One year of experience utilizing EDA methodologies including Tcl, LEX, and YACC.
• One year of experience in Cadence SKILL language development.
• One year of experience with VLSI verification methodologies using SystemVerilog and Universal Verification Methodology (UVM).
• One year of experience with hardware description languages such as Verilog and VHDL.
• One year of experience in EDA software tool development and EDA-focused AI development.