Custom SOC IP Verification Engineer

Nvidia

Quick summary

Work type: On-site
Location: Santa Clara, CA · Austin, TX
Salary: $168,000–$264,500 / yr
Posted: 59 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $191k

This role $216k

$135k most similar roles pay here $278k

This role pays more than 79% of similar roles. Most pay $165,150–$216,250 — the shaded band above. At the midpoint, this role pays about $216k versus about $191k for comparable roles.

Based on 240 similar postings.

Employer

About Nvidia

Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing

Nvidia currently has 985 open roles on FindRole.

Listed pay typically runs $184,000–$287,500 across 971 roles with salary data.

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At a glance

TL;DR · Custom SOC IP Verification Engineer

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NVIDIA seeks a Senior Custom SOC/IP Verification Engineer to join its cutting-edge team, focusing on verifying next-generation SoCs and IP solutions. This role involves developing comprehensive test plans for cache coherency verification using UVM environments, designing System Verilog testbenches for complex memory hierarchies, and collaborating with cross-functional teams to ensure robust verification strategies. The ideal candidate will have 8+ years of experience in ASIC verification, particularly in cache coherency or memory subsystems, along with expertise in System Verilog, UVM, and C++. Knowledge of AMBA protocols like AXI, ACE, and CHI is essential, as is familiarity with SoC architectures and CPU-cache interactions. Additionally, proficiency in scripting languages such as Python and TCL, and experience with formal verification or assertion-based verification (SVA), enhances the candidate's suitability for this role within NVIDIA’s high-scale semiconductor design environment.

Skills

SystemVerilog UVM C++ Python Perl TCL RISC-V ARM AMBA AXI ACE CHI Cache Coherency ASIC Verification Formal Verification SVA GPU-Based Verification Palladium Veloce

What you'll do

Develop test plans for cache coherency verification of ASIC-based SoCs using UVM environments.
Design and implement System Verilog testbenches targeting multi-level cache hierarchies and interconnect fabrics.
Ensure comprehensive first-time right verification by collaborating with cross-functional teams.
Drive the development of silicon and platform verification strategies and methodologies.
Maintain deep knowledge of System Verilog, UVM, and C++ for ASIC verification.

What we're looking for

8+ years of ASIC verification experience, focusing on cache coherency protocols and memory subsystems.
Expertise in System Verilog, UVM methodology, and AMBA protocols including AXI, ACE, CHI.
Strong background in SoC architectures, memory models, and CPU-cache interactions.
Proficiency in scripting languages (Python, Perl, TCL) and C/C++ for testbench integration.
Familiarity with formal verification or assertion-based verification techniques using SVA.
Knowledge of RISC-V or ARM architecture and system-level cache subsystems preferred.
Experience with coherency modeling tools, verification IPs, and emulation platforms beneficial.

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