Careers
Quick summary
- Work type
- On-site
- Location
- San Diego, CA
- Posted
- 52 days ago
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $152,075–$208,800.
Based on 239 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 660 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 429 roles with salary data.
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At a glance
TL;DR · Careers
As a Senior Design Verification Engineer at Qualcomm, you will join the ASIC verification team to ensure that IPs, subsystems, and SoCs meet stringent power, performance, and area goals for Wi-Fi, connectivity, and IoT platforms. Your responsibilities include defining and improving verification methodologies, exploring innovative techniques like simulation, formal verification, and emulation, and owning end-to-end low-power verification processes. You will collaborate with cross-functional teams globally to deliver high-quality IPs and SoCs while serving as a technical point of contact for design teams. The role requires expertise in SystemVerilog, UVM-based verification methodologies, C/C++, assembly language, and scripting languages like Python or Perl, along with a solid understanding of AMBA bus protocols and low-power design concepts.
Skills
What you'll do
- Develop and apply innovative design verification methodologies for IPs and SoCs.
- Own end-to-end low-power verification including testbench architecture and coverage-driven closure.
- Define and improve verification processes and tools for large, complex IPs and subsystems.
- Serve as a technical point of contact, providing verification guidance to IP and SoC teams.
- Collaborate on cross-geography deliveries, planning milestones and conducting critical debug activities.
What we're looking for
- 3+ years of ASIC design verification experience, including complex SoC subsystems or IP blocks.
- Expertise in SystemVerilog and UVM-based methodologies for assertion-based and coverage-driven verification.
- Strong analytical skills and proficiency in test automation, constrained-random testing, and code/functional coverage.
- Experience with C/C++ and assembly language for test development, modeling, or debug.
- Knowledge of AMBA bus protocols (AXI, AHB, APB) and low-power design concepts.
- Proficiency in scripting languages like Python or Perl for automation and productivity.
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