Careers
Quick summary
- Work type
- On-site
- Location
- Santa Clara, CA · Austin, TX
- Posted
- 26 days ago
- Closes
- Nov 7, 2026
- Nearby
- 99+ roles within 25 mi
Market check
Salary context
How this pay compares to similar roles
This listing doesn't post a salary. Most similar roles pay $152,037–$208,800.
Based on 238 similar postings.
Employer
About Qualcomm
Qualcomm is a leading American semiconductor and telecommunications company based in San Diego, CA.
Qualcomm currently has 558 open roles on FindRole.
Listed pay typically runs $154,000–$231,000 across 401 roles with salary data.
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At a glance
TL;DR · Careers
As an ASIC Design Verification Engineer at Qualcomm Technologies, Inc., you will join a dynamic team responsible for the entire verification lifecycle of digital power IPs, from concept to post-silicon support. Your daily tasks will include comprehensive test planning, developing advanced SystemVerilog-UVM testbenches, creating coverage and assertion models, and conducting formal verification. You will also work on automating processes to enhance verification efficiency and gain experience with power-aware UPF verification methodologies. The role requires a minimum of three years of DV experience using UVM and assertion-based technologies, familiarity with SOC or subsystem verification, and knowledge of DDR memory protocols and VIPs. Additionally, exposure to formal verification, PASIM simulations, and C++ firmware development is essential. This position offers the opportunity to contribute to cutting-edge technology in the semiconductor industry, working on complex systems like DDR and cache modules.
Skills
What you'll do
- Develop comprehensive pre-silicon test plans for digital power IP.
- Create advanced verification methodologies using SystemVerilog-UVM and formal verification techniques.
- Design assertion models to ensure robust verification coverage.
- Implement automation tools to enhance verification efficiency and accuracy.
- Collaborate on the development of power-aware UPF verification flows.
What we're looking for
- Minimum 3 years of DV experience using UVM and assertion-based verification.
- Experience verifying complex SoC or subsystems with caches and DDR memory protocols.
- Familiarity with memory verification VIPs and formal verification techniques.
- Successful tapeout experience from conception to post-silicon debug.
- Proficiency in SystemVerilog, C++, Python for automation and testbench development.
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