CAD Engineer, Custom EMIR Methodology

Apple Inc

Confirmed live yesterday High trust

Quick summary

Work type: On-site
Location: —
Salary: $142,300–$263,300 / yr
Posted: 15 days ago
Freshness: Confirmed live yesterday

Market check

Salary context

Competitive pay

How this pay compares to similar roles

Similar $205k

This role $203k

$128k most similar roles pay here $279k

This role pays less than 55% of similar roles. Most pay $168,500–$241,750 — the shaded band above. At the midpoint, this role pays about $203k versus about $205k for comparable roles.

Based on 240 similar postings.

Employer

About Apple Inc

Apple Inc. is a multinational technology company known for designing and manufacturing consumer electronics, software, and online services, including the iPhone, Mac, iPad, and App Store. Industry: Consumer Electronics & Software

Apple Inc currently has 3513 open roles on FindRole.

Listed pay typically runs $165,800–$277,600 across 2730 roles with salary data.

Most-posted roles

View all roles at Apple Inc

At a glance

TL;DR · CAD Engineer, Custom EMIR Methodology

Role Posting Log in to save

As a CAD Engineer - Custom EMIR Methodology, you will join the CAD Group to develop and refine state of the art designs. You will be responsible for supporting transistor level power/signal EM and IR solutions that scale with accuracy and capacity challenges while enhancing custom transistor level EM/IR methodologies. The role involves collaborating with physical-design, integration, circuit-design, power, and technology groups to address circuit verification requirements across various processes. You will partner with design, CAD, and EDA teams to identify flow deficiencies and deliver advanced solutions. Required skills include proficiency in Python, Perl, or C/C++, along with experience in custom design environments involving schematic/layout design, simulation, extraction, and physical verification. You will use your expertise in EM/IR analysis tools and automation to solve complex technical challenges and drive methodology advancements for transistor level designs.