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Python C++ Perl Ruby PCIe CXL DDR Memory RAS MCA MCE JTAG SCAN Protocol Analyzers Post Silicon Validation X86 micro architecture Debug Scripts SOC Micro-Controller +13 more Show less

Embedded Linux Yocto PetaLinux SystemVerilog Verilog VHDL Vivado Vitis Python C C++ Tcl Shell JTAG DDR5 LPDDR5 FPGA SoC Static Timing Analysis +14 more Show less

ASIC Design SoC Architecture RTL Design Verilog SystemVerilog FPGA Design Emulation Hardware Validation Hardware Debug C/C++ Python Tcl Perl Linux Embedded Linux CI/CD JTAG Git JIRA PCIe AXI Ethernet I2C Palladium Veloce MBIST ATPG +22 more Show less

Server Systems Debug SoC C/C++ Python Perl Ruby System Architecture Firmware Logic Analyzers Oscilloscopes Validation Strategy Scripting Bring-up +8 more Show less

Python Bash Ansible UEFI DHCP DNS PXE Netboot SoC Firmware Failure Analysis Kernel Logs System Logs Configuration Management Infrastructure Provisioning Benchmarking Frameworks Electrical Engineering HPC Server Architecture +14 more Show less

GPU Architecture SoC C/C++ Python Shell Perl PCIe HBM Firmware System Bring-up Validation Root-cause Analysis Oscilloscopes Git Agile Cloud Infrastructure Networking +12 more Show less