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RTL Methodology Silicon Design Engineer

Amd

Austin, TX 11 days ago $178,400–$267,600
Actively hiring Confirmed live today High trust Above market
RTL Design SystemVerilog Verilog Python Go Java C# TypeScript Perl Ruby Shell TCL LLM RAG Agentic Frameworks Static Analysis Linting Verible Slang Verilator Surelog Synthesis Physical Design Place and Route Timing Closure
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