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Analog/Mixed Signal Verilog Modeling Design Engineer

Broadcom

Irvine, CA +1 117 days ago
Actively hiring Confirmed live 2 days ago High trust
SystemVerilog Verilog-AMS Cadence ncsim xrun vcs Python TCL Perl RTL Testbench Analog Circuits SARADC FSM Cursor chipAgents
8+ yrs exp
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