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Senior ASIC Physical Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 32 days ago $136,000–$218,500
Actively hiring Confirmed live 2 days ago High trust Competitive pay
Physical Design Synthesis Timing Analysis Floor-planning Verilog ASIC Design Flow RTL Design Verification DFT ECO High-frequency Design Micro-architecture
5+ yrs exp
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Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 177 days ago $136,000–$218,500
Actively hiring Confirmed live yesterday Trusted Competitive pay
Verilog RTL ASIC Design Flow Logic Synthesis Timing Closure Computer Architecture Cache Coherency high speed interconnects DFT Floor-planning ECO Lab Debug
5+ yrs exp Hybrid
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