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Active Keyword: Senior Logic Design Engineer Remove filter Location: Santa Clara Remove filter Clear all

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Senior Logic Design Engineer, Cache Coherent Interconnects

Nvidia

Santa Clara, CA +1 5 days ago $136,000–$218,500
Actively hiring Confirmed live today Posted this week High trust Competitive pay
Verilog RTL Design ASIC Design Flow Logic Synthesis Timing Closure DFT Timing Analysis Floor-planning ECO Computer Architecture Cache Coherency Logic Debug Prototyping Bring-up Lab Debug
5+ yrs exp Hybrid
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