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Active Keyword: ASIC Physical Design and Timing Engineer Remove filter Location: Santa Clara Remove filter Clear all

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ASIC Physical Design and Timing Engineer, New College Grad 2026

Nvidia

Santa Clara, CA 2 days ago $116,000–$189,750
Actively hiring Posted this week Verified listing Below market
STA EDA tools Timing Constraints Synthesis Equivalence Checking Floor-planning Physical Design Deep Sub-micron Process Nodes AI/LLM Python C++ Perl Tcl Shell Scripting
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