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Active Keyword: SerDes RTL Design Engineer Remove filter Location: San Jose Remove filter Clear all

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SerDes RTL Design Engineer

Amd

San Jose, CA 22 days ago $166,400–$249,600
Actively hiring Confirmed live today High trust Competitive pay
RTL Verilog System Verilog SerDes PMA PCS Python Perl TCL CMOS Static Timing Analysis LINT CDC RDC Digital Signal Processing Low Power Design Mixed Signal Design PPA Analysis
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