As a Senior Mask Layout Design Engineer, you will join our dynamic and growing team of experts responsible for high-speed mixed-signal circuit designs. Your daily tasks will involve collaborating with circuit designers and mask designers to perform physical layout for digital and mixed-signal functions such as clock generators, op-amps, sensors, security circuits, and power delivery circuits using Cadence tools in state-of-the-art sub-micron CMOS technologies. You will work closely with ASIC and mixed-signal engineers to customize designs for integration into VLSI products, handle floor planning and custom layout, verify against design rules and schematics, manage DRC mitigation, and interact with foundries. Essential skills include a BS in Electrical Engineering or equivalent experience, at least 7 years of hands-on layout design experience, proficiency in Cadence tools like Virtuoso, and knowledge of verification tools such as Dracula, Hercules, and Calibre. Additionally, you should have leadership experience mentoring junior designers, strong communication skills for cross-geography teams, and familiarity with scripting languages like Perl, Python, and Skill.
Perform physical layout for digital and mixed-signal functions using Cadence tools.
Customize designs for integration in VLSI products with ASIC and mixed-signal engineers.
Conduct floor planning, custom layout verification against design rules and schematics.
Execute fill, post-processing, DRC mitigation, and engage in foundry interactions.
Mentor junior mask designers and implement standard processes for optimal layout.
What we're looking for
At least 7+ years of hands-on layout design experience in submicron CMOS technologies.
Deep understanding and practical use of Cadence custom circuit design tools like Virtuoso.
Experience running and debugging DRC and LVS using verification tools such as Dracula, Hercules, Calibre.
Leadership skills including mentoring junior designers and implementing standard processes.
Strong communication abilities for collaborating with diverse teams across geographies.
Proficiency in scripting languages like Perl, Python, or Skill (preferred).
Knowledge of layout automation techniques.
Market check
Salary context
This
$132,000–$207,000
range sits above
48%
of similar postings on FindRole.
Peer median band
$119,500–$218,500
Median floor and ceiling across peers.
Typical midpoint (25–75%)
$142,400–$198,412
Middle half of comparable postings.
Based on 240 comparable postings.*
* 240 is the maximum number of comparable postings sampled.
Employer
About Nvidia
Nvidia is a leading designer of graphics processing units (GPUs) and system-on-chip units, powering gaming, professional visualization, data centers, and artificial intelligence workloads. Industry: Semiconductors & AI Computing
Nvidia currently has
801 open roles
on FindRole.
Listed pay typically runs
$184,000–$287,500
across 797 roles with salary data.
Us, Ca, Santa Clara, US119 days ago
$168,000–$264,500
Spice
Python
Perl
Tcl
Make
RTL
Logic Synthesis
Verification
Auto Place and Route
STA
PnR
DRC
LVS
Power Gating
Multi-Vt
Post-Silicon Characterization
Custom Circuit Design
Semi-Custom Circuit Design
Us, Ca, Santa Clara, US31 days ago
$168,000–$264,500
Python
TCL
JavaScript
TypeScript
NodeJS
Git
JIRA
Confluence
CI
Perforce
Oracle
MySQL
MongoDB
Cadence System Capture TCL API
Cadence SKILL
PLM systems
Windows
Linux