Senior FPGA Verification Engineer

Anduril Industries

Quick summary

Work type
On-site
Location
Costa Mesa, CA
Salary
$146,000–$220,000 / yr
Posted
today

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Competitive pay

How this pay compares to similar roles

Similar $189k
This role $183k
$137k most similar roles pay here $234k

This role pays less than 55% of similar roles. Most pay $161,500–$216,250 — the shaded band above. At the midpoint, this role pays about $183k versus about $189k for comparable roles.

Based on 240 similar postings.

Employer

About Anduril Industries

Anduril Industries is a defense technology company that builds advanced hardware and software systems for national security, including autonomous drones, surveillance systems, and the Lattice AI command platform.

Anduril Industries currently has 1882 open roles on FindRole.

Listed pay typically runs $146,000–$194,000 across 1696 roles with salary data.

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At a glance

TL;DR · Senior FPGA Verification Engineer

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The Senior/Staff FPGA Verification Engineer role is part of the Air Dominance and Strike (AD&S) Electrical Engineering Team at Anduril, responsible for developing high-reliability avionics systems. This position involves leading verification strategy and methodology for AMD (Xilinx) platforms, including defining UVM architecture, mentoring engineers, and driving tooling roadmaps. Key responsibilities include architecting UVM environments, developing verification plans, and ensuring compliance with DO-254 standards. The ideal candidate should have extensive experience in FPGA/ASIC verification using SystemVerilog, UVM, and SVA, along with proficiency in simulators like Questa and VCS, Git workflows, and CI/CD integration. This role demands expertise in safety-critical systems for autonomous air platforms.

Skills

SystemVerilog UVM SVA Questa VCS Xcelium Git Linux Python Tcl Makefile SVUnit Formal verification CDC verification CI/CD Nix DO-254

What you'll do

  • Define UVM architecture and reusable verification component libraries for FPGA/SoC designs.
  • Mentor verification engineers by reviewing testbenches, plans, and coverage models.
  • Develop SystemVerilog Assertions (SVA) for protocol compliance and design intent checks.
  • Build functional coverage models to drive code coverage analysis to closure.
  • Establish regression suites and track coverage metrics for verification progress.

What we're looking for

  • 7+ years of experience in FPGA/ASIC verification
  • Proficient in SystemVerilog, UVM methodology, and SVA
  • Track record owning verification closure on production or flight programs
  • Experience defining verification methodology and mentoring engineers
  • Eligible to obtain and hold a U.S. Secret security clearance
  • Industry simulator expertise (Questa, VCS, Xcelium, Vivado)
  • Verification automation scripting skills (Python, Tcl, Makefile)

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