| Microsoft Careers

Microsoft

Quick summary

Work type
On-site
Location
—
Salary
$142,800–$274,800 / yr
Posted
60 days ago

Market check

Salary context

Above market

How this pay compares to similar roles

Similar $180k
This role $209k
$101k most similar roles pay here $293k

This role pays more than 95% of similar roles. Most pay $152,150–$207,350 — the shaded band above. At the midpoint, this role pays about $209k versus about $180k for comparable roles.

Based on 239 similar postings.

Employer

About Microsoft

Microsoft Corporation is a global technology leader producing software, hardware, and cloud services including Windows, Office 365, Azure cloud platform, Xbox gaming, and Surface devices. Industry: Software & Cloud Computing

Microsoft currently has 1580 open roles on FindRole.

Listed pay typically runs $119,800–$234,700 across 1408 roles with salary data.

Most-posted roles

View all roles at Microsoft

At a glance

TL;DR · | Microsoft Careers

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The Principal Engineer for Technology and Foundry Interface role within the Foundry and Advanced Packaging team requires a senior-level engineer with extensive experience in semiconductor process development and manufacturing. This individual will lead technical interactions with external foundries, ensuring best-in-class silicon performance through pre-silicon design, post-silicon development, and continuous improvement during production. Daily responsibilities include compiling data using statistical techniques, defining engineering structures for technology interception, and conducting comprehensive power, performance, area, and cost analyses. The ideal candidate possesses deep knowledge of device physics, process qualification, and yield improvement techniques, along with experience in EDA tools such as Cadence, Caliber, Synopsys, and Siemens. Familiarity with coding languages like Python, Java, and C++, as well as AI/ML optimization, is essential for driving innovation in cloud hardware manufacturing at Microsoft.

Skills

Python Java C++ EDA_tools_Cadence EDA_tools_Synopsys EDA_tools_Siemens AI/ML DFT DFM DOE STA RTL_to_GDS PPA_optimization SOC_design_features ATE_test_program_methodologies

What you'll do

  • Lead technical interactions with external foundries throughout the silicon lifecycle.
  • Compile and analyze data using statistical methods for yield optimization.
  • Define engineering structures in test chips for technology enablement and analysis.
  • Provide comprehensive Power, Performance, Area, and Cost (PPAC) analysis for new technologies.
  • Support design teams with PDKs, IP development, and DFM requirements implementation.

What we're looking for

  • 9+ years of technical engineering experience or equivalent education/experience combination
  • Extensive experience in semiconductor process development and manufacturing (8+ years)
  • Deep expertise in technology evaluation, testchip design, and modeling (5+ years)
  • Strong understanding of device physics, foundry design management, and yield improvement techniques
  • Experience supporting design teams with PDKs, IP development, and DFM requirements
  • Proficiency in EDA tools from Cadence, Caliber, Synopsys, Siemens for device and IP study
  • Ability to lead cross-functional teams and manage projects effectively

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