| Microsoft Careers

What you'll do

• Own and architect the end-to-end silicon signoff CAD flow strategy, ensuring production-quality convergence.
• Drive quality improvements by establishing best practices and systematic validation frameworks to prevent silicon escapes.
• Lead technical engagement with EDA vendors to evaluate, qualify, and deploy new signoff tool versions.
• Ensure seamless integration between implementation and signoff for multiple concurrent silicon programs.
• Establish technical standards and conduct design reviews to foster continuous improvement in the team.

What we're looking for

• 10+ years of experience in silicon signoff CAD engineering.
• Extensive hands-on experience with parasitic extraction and static timing analysis tools at advanced process nodes (5nm and below).
• Familiarity with physical design implementation tools from both Synopsys and Cadence ecosystems.
• Strong scripting skills in TCL and Python for developing production signoff flows.
• Track record of leading multiple concurrent tapeouts with zero-escape silicon quality.
• Experience evaluating competitive EDA solutions and driving best-in-class tool selection.
• Record of technical growth in teams, establishing scalable flow architectures.