IP Integration Engineer

What you'll do

• Develop a detailed understanding of Broadcom's die-to-die PHYs.
• Optimize size and power delivery for high IO density PHYs with analog teams.
• Analyze power integrity issues in various use cases and workloads.
• Write comprehensive documentation for integrating PHY IP into ASICs.
• Collaborate with physical composition teams on 2.5D and 3.5D ASIC integration.
• Develop quality checklists to ensure the reliability of PHY IPs.
• Support customer inquiries related to PHY integration and issues.

What we're looking for

• Bachelor’s Degree in Electrical or Computer Engineering, 5+ years related experience; or Master's degree, 3+ years related experience.
• Proficient in Cadence Innovus toolset and understanding of modern FET architecture including FinFET and GAA topologies.
• Strong knowledge of ASIC design flow including RTL, synthesis, timing analysis, floorplanning, power planning, P&R, LVS, DRC.
• Excellent verbal and written communication skills with ability to work effectively in a team environment.
• Capable of multitasking, managing multiple technical issues simultaneously, and meeting strict project deadlines.
• Experience reading and interpreting timing reports from static timing tools like Tempus or Primetime.